The present invention relates to the field of semiconductor processing and more particularly to a process simulation method that allows a semiconductor device design to be evaluated for critical dimension and alignment/registration variations prior to fabrication.
An integrated circuit is fabricated by translating a circuit design or layout to a semiconductor substrate. In optical lithography, the layout is first transferred onto a physical template, which is in turn, used to optically project the layout onto a silicon wafer. In transferring the layout to a physical template, a mask is generally created for each layer of the integrated circuit design. The patterned photomask includes transparent, attenuated phase shifted, phase shifted, and opaque areas for selectively exposing regions of the photoresist-coated wafer to an energy source. To fabricate a particular layer of the design, the corresponding mask is placed over the wafer and a stepper or scanner machine shines a light through the mask via the energy source. The end result is a semiconductor wafer coated with a photoresist layer having the desired pattern that defines the geometries, features, lines and shapes of that layer. The photolithography process is typically followed by an etch process during which the underlying substrate not covered or masked by the photoresist pattern is etched away, leaving the desired pattern in the substrate. This process is then repeated for each layer of the design.
Ideally, the photoresist pattern produced by the photolithography process and the substrate pattern produced by the subsequent etch process would precisely duplicate the pattern on the photomask. For a variety of reasons, however, the photoresist pattern remaining after the resist develop step may vary from the pattern of the photomask significantly. Diffraction effects and variations in the photolithography process parameters typically result in critical dimension (CD) variation from line to line depending upon the line pitch surrounding environment (where pitch is defined for purposes of this disclosure as the displacement between an adjacent pair of interconnect lines). In addition to CD variation, fringing effects and other process variations can result in end-of-line effects (in which the terminal end of an interconnect line in the pattern is shortened or cut off by the photolithography process) and corner rounding (in which square angles in the photomask translate into rounded corners in the pattern). These three primary optical proximity effects, together with other photoresist phenomena such as notching, combine to undesirably produce a patterned photoresist layer that may vary significantly from the pattern of the photomask. In addition to variations introduced during the photolithography process, further variations and distortions are typically introduced during the subsequent etch process such that the pattern produced in the semiconductor substrate may vary from the photomask pattern even more than the photoresist pattern.
Conventional semiconductor process engineering in the areas of photolithography and etch typically attempts to obtain a finished pattern that more closely approximates the desired pattern as closely as possible by controllably altering the process parameters associated with the various masking steps. Among the parameters process engineers typically attempt to vary in an effort to produce a photoresist pattern substantially identical to the photomask pattern include the intensity, coherency and wave length of the energy source, the type of photoresist, the temperature at which the photoresist is heated prior to exposure (pre-bake), the dose (intensityxc3x97time) of the exposing energy, the numerical aperture of the lens used in the optical aligner, the use of antireflective coatings, the develop time, developer concentration, developer temperature, developer agitation method, post bake temperature, and a variety of other parameters associated with the photolithography process. Etch parameters subject to variation may include, for example, process pressure and temperature, concentration and composition of the etch species, and the application of a radio frequency energy field within the etch chamber.
Despite their best efforts, however, semiconductor process engineers are typically unable to manipulate the photolithography and etch processes such that the photoresist and substrate patterns produced by the processes are substantially identical to the photomask pattern.
To avoid the time and cost of producing actual test wafers for every desired permutation of process parameters, computerized simulation of masking processes is employed to facilitate the optimization of a particular masking sequence and the generation of an optical proximity correction (OPC) distorted photomask. Masking process simulators receive various inputs corresponding to the parameters of the photoresist and etch processes to be simulated and attempt to simulate the pattern that will be produced by the specified masking process given a particular photomask. Accordingly, computerization has significantly enhanced the process engineer""s ability to characterize and optimize masking processes.
Nevertheless, it is typically impossible to adequately account for the multitude of parameters associated with a masking process despite the effort devoted to masking process characterization, the introduction of optical proximity correction techniques, and the emergence of sophisticated process simulation software. For example, all stepper machines have critical dimension (CD) and alignment/registration tolerances. These tolerances indicate how much a printed feature may deviate from a mathematically perfect image. For instance, the specification for a particular scanner may specify that the tolerance for alignment and registration is xc2x130 nanometers, while the tolerance for the critical dimension (CD) or line width control is xc2x115 nanometers. In addition, these tolerances may be different for each layer of the semiconductor device.
Alignment/registration and CD errors in a device become significant because errors on different layers compound each other. For example, assume that the scanner tolerances for a particular contact layer states that contacts can be misaligned by xc2x125 nanometers. If for example, the contact layer is misaligned by 25 nanometers to the left when the device is made, and the feature that the contact is to overlap with on an adjacent layer is misaligned to the right by the same amount, the contact may fail to overlap with that feature. To allow for this variation, the device designer may have to design the contact 50 nanometers larger to ensure the contacts will always overlap with the other feature when the device is made, thus decreasing packing density of the device.
Although conventional simulation programs are capable of simulating the result of different layers in the device, such programs are incapable of allowing the device designer to easily evaluate all the possible process variations that may occur due to CD and alignment/registration errors, and the effects of those variations on adjacent layers of the device.
Accordingly, what is needed is a method and system for improving the simulation software to allow a multi-layer semiconductor device design to be evaluated for critical dimension and alignment/registration variations without having to actually fabricate the semiconductor. The present invention addresses such a need.
The present invention provides an improved process simulation system for simulating results of fabrication process for a semiconductor device design. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After the simulation, the process simulator superimposes the aerial images to create a composite image, and displays the composite image to an operator. The operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values.
According to the method and system disclosed herein, the process simulator allows the operator or device designer to predict with a high degree of accuracy the nominal capability of the fabrication process and also investigate normal process fluctuations occurring in scanner alignment/registration and critical dimension control. The present invention may further be used at the mask level to see the effects of inherent mask misalignment issues and their effects on the chip making process.